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Silicon Labs /EFR32MG24A121F1536GM48 /RAC_S /SYLOEN

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Interpret as SYLOEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)SYLODIVEN 0 (disable)SYLODIVLDOBIASEN 0 (disable)SYLODIVLDOEN 0 (disable)SYLODIVRLOADCCLK2G4EN 0 (disable)SYLODIVTLO0DBM2G4AUXEN 0 (disable)SYLODIVTLO0DBM2G4EN 0 (disable)SYLODIVTLO20DBM2G4AUXEN 0 (disable)SYLODIVTLO20DBM2G4EN 0 (adc_clk_div8)SYLODIVRLOADCCLKSEL

SYLODIVLDOBIASEN=disable, SYLODIVEN=disable, SYLODIVTLO0DBM2G4AUXEN=disable, SYLODIVTLO20DBM2G4AUXEN=disable, SYLODIVTLO20DBM2G4EN=disable, SYLODIVTLO0DBM2G4EN=disable, SYLODIVRLOADCCLK2G4EN=disable, SYLODIVLDOEN=disable, SYLODIVRLOADCCLKSEL=adc_clk_div8

Fields

SYLODIVEN

SYLODIVEN

0 (disable): undefined

1 (enable): undefined
SYLODIVLDOBIASEN

SYLODIVLDOBIASEN

0 (disable): undefined

1 (enable): undefined
SYLODIVLDOEN

SYLODIVLDOEN

0 (disable): undefined

1 (enable): undefined
SYLODIVRLOADCCLK2G4EN

SYLODIVRLOADCCLK2G4EN

0 (disable): undefined

1 (enable): undefined
SYLODIVTLO0DBM2G4AUXEN

SYLODIVTLO0DBM2G4AUXEN

0 (disable): undefined

1 (enable): undefined
SYLODIVTLO0DBM2G4EN

SYLODIVTLO0DBM2G4EN

0 (disable): undefined

1 (enable): undefined
SYLODIVTLO20DBM2G4AUXEN

SYLODIVTLO20DBM2G4AUXEN

0 (disable): undefined

1 (enable): undefined
SYLODIVTLO20DBM2G4EN

SYLODIVTLO20DBM2G4EN

0 (disable): undefined

1 (enable): undefined
SYLODIVRLOADCCLKSEL

SYLODIVRLOADCCLKSEL

0 (adc_clk_div8): undefined

1 (adc_clk_div16): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data